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DATA SHEET
512MB Unbuffered SDRAM S.O.DIMM
HB52RF649DC-B (64M words x 72 bits, 2 bank) HB52RD649DC-B (64M words x 72 bits, 2 bank)
Description
The HB52RF649DC, HB52RD649DC are a 64M x 72 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 18 pieces of 256M bits SDRAM sealed in TCP package and 1 piece of serial EEPROM (2k bits) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
Features
* Fully compatible with: JEDEC standard outline 8 bytes S.O.DIMM * 144-pin Zig Zag Dual tabs socket type (dual lead out) PCB height: 33.02mm (1.30inch) Lead pitch: 0.80mm * 3.3V power supply * Clock frequency: 133MHz/100MHz (max.) * LVTTL interface * Data bus width: x 72 ECC * Single pulsed /RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8 * 2 variations of burst sequence Sequential Interleave * Programmable /CE latency (CL): 2, 3 * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current : HB52RF649DC-xxBL (L-version) : HB52RD649DC-xxBL (L-version)
Document No. E0223H30 (Ver. 3.0) Date Published April 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52RF649DC-B, HB52RD649DC-B
Ordering Information
Part number HB52RF649DC-75B*1 HB52RF649DC-75BL*1 HB52RD649DC-A6B*1 HB52RD649DC-A6BL*1 Clock frequency MHz (max.) 133 MHz 133 MHz 100 MHz 100 MHz /CE latency 3 3 2, 3 2, 3 Package 144-pin S.O.DIMM Contact pad Gold Mounted devices 256M bits SDRAM TCP*2
Notes: 1. 100MHz operation at /CE latency = 2. 2. Please refer to the TSOP products HM5225XX5B datasheet (E0082H) for detail information.
Pin Configurations
Front Side
1pin 2pin
59pin 60pin
61pin 62pin
143pin 144pin
Back Side
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS Pin No. 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 Pin name NC VSS CB2 CB3 VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS
Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 A4 A5 VSS Pin No. 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 Pin name CK1 VSS CB6 CB7 VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS
Data Sheet E0223H30 (Ver. 3.0)
2
HB52RF649DC-B, HB52RD649DC-B
Front side Pin No. 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin name DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS CB0 CB1 CK0 VCC /RE /W /S0 /S1 Pin No. 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Pin name A9 A10 (AP) VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC Back side Pin No. 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin name DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS CB4 CB5 CKE0 VCC /CE CKE1 A12 NC Pin No. 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Pin name BA1 A11 VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
Pin Description
Pin name A0 to A12 Function Address input Row address Column address A0 to A12 A0 to A9
BA0, BA1 DQ0 to DQ63 CB0 to CB7 /S0, /S1 /RE /CE /W DQMB0 to DQMB7 CK0, CK1 CKE0, CKE1 SDA SCL VCC VSS NC
Bank select address Data-input/output Check bit (Data-input/output) Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground No connection
Data Sheet E0223H30 (Ver. 3.0)
3
HB52RF649DC-B, HB52RD649DC-B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels SDRAM cycle time (highest /CE latency) (-75) 7.5ns (-A6) 10ns
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 80 08 04 0D 0A 02 48 00 01 75 A0 54 60 02 82 08 08 01 0F 04 06 01 01 00 0E A0
Comments 128 256byte SDRAM 13 10 2 72 0 (+) LVTTL CL = 3
10
SDRAM access from Clock (highest /CE latency) 0 (-75) 5.4ns (-A6) 6ns 0 0 1 0 0 0 0 0 0 0 0 0 0 1
11 12 13 14 15 16 17 18 19 20 21 22 23
Module configuration type Refresh rate/type SDRAM width Error checking SDRAM width SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CE latency SDRAM device attributes: /S latency SDRAM device attributes: /W latency SDRAM module attributes SDRAM device attributes: General SDRAM cycle time (2nd highest /CE latency) 10ns SDRAM access from Clock (2nd highest /CE latency) 6ns SDRAM cycle time (3rd highest /CE latency) Undefined
ECC Normal (7.8125s) Self refresh x8 x8 1 CLK 1, 2, 4, 8 4 2, 3 0 0 Unbuffer VCC 10% CL = 2
24
0
1
1
0
0
0
0
0
60
25
0
0
0
0
0
0
0
0
00
Data Sheet E0223H30 (Ver. 3.0)
4
HB52RF649DC-B, HB52RD649DC-B
Byte No. 26 27 28 Function described SDRAM access from Clock (3rd highest /CE latency) Undefined Minimum row precharge time Row active to row active min (-75) (-A6) 29 30 /RE to /CE delay min Minimum /RE pulse width (-75) (-A6) 31 32 Density of each bank on module Address and command signal input setup time (-75) (-A6) 33 Address and command signal input hold time (-75) (-A6) 34 Data signal input setup time (-75) (-A6) 35 Data signal input hold time (-75) (-A6) 36 to 61 62 63 Superset information SPD data revision code Checksum for bytes 0 to 62 (-75) (-A6) 64 65 to 71 72 73 74 75 76 77 78 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-75) (-A6) 79 80 81 82 83 84 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 x 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 x 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 x 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 x 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 x 0 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 x 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 x 0 0 1 0 0 0 0 0 0 1 0 1 1 00 14 0F 14 14 2D 32 40 15 20 08 10 15 20 08 10 00 12 5D C4 07 00 xx 48 42 35 32 52 46 44 36 34 39 44 43 2D *2 (ASCII-8bit code) H B 5 2 R F D 6 4 9 D C 20ns 15ns 20ns 20ns 45ns 50ns 256M byte 1.5ns 2.0ns 0.8ns 1.0ns 1.5ns 2.0ns 0.8ns 1.0ns Future use Rev. 1.2B 93 196 HITACHI Comments
Data Sheet E0223H30 (Ver. 3.0)
5
HB52RF649DC-B, HB52RD649DC-B
Byte No. 85 Function described Manufacturer's part number (-75) (-A6) 86 Manufacturer's part number (-75) (-A6) 87 88 Manufacturer's part number Manufacturer's part number (-xxB) (-xxBL) 89 90 91 92 93 94 95 to 98 99 to 125 126 127 Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Assembly serial number Manufacturer specific data Intel specification frequency Intel specification /CE# latency support Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 x x *
3
Comments 7 A 5 6 B (Space) L (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD) *4 100MHz CL = 2, 3
0 1 0 0 1 0 1 0 0 0 0 x x
1 0 1 1 0 1 0 1 1 1 1 x x
1 0 1 1 0 0 0 0 0 1 0 x x
0 0 0 0 0 0 1 0 0 0 0 x x
1 0 1 1 0 0 1 0 0 0 0 x x
1 0 0 1 1 0 0 0 0 0 0 x x
1 1 1 0 0 0 0 0 0 0 0 x x
37 41 35 36 42 20 4C 20 20 30 20 xx xx
-- 0 1
-- 1 1
-- 1 0
-- 0 0
-- 0 1
-- 1 1
-- 0 1
-- 0 1
-- 64 CF
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High". These SPD are based on Rev.1.2B specification. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0").
Data Sheet E0223H30 (Ver. 3.0)
6
HB52RF649DC-B, HB52RD649DC-B
Block Diagram
A0 to A12, BA0, BA1 /RE, /CE, /W /S1 /S0 /CS DQMB0 DQ0 to DQ7 DQM 8 N0, N1 I/O0 to I/O7 /CS /CS DQMB4 /CS
D0
DQM I/O0 to I/O7
D9
DQ32 to DQ39
DQM 8 N10, N11 I/O0 to I/O7
D5
DQM I/O0 to I/O7
D14
/CS DQMB1 8 DQ8 to DQ15 RA0 to RA12, RBA0, RBA1 /RRE, /RCE, /RW /CS DQM CB0 to CB7 A0 to A12, BA0, BA1 /RE, /CE, /W /CS DQMB2 DQ16 to DQ23 DQM 8 N6, N7 I/O0 to I/O7 8 N4, N5 I/O0 to I/O7 N2, N3 DQM I/O0 to I/O7
/CS
/CS DQMB5
/CS
D1
DQM I/O0 to I/O7
D10
DQ40 to DQ47
DQM N12, 8 N13 I/O0 to I/O7
D6
DQM I/O0 to I/O7
D15
/CS DQM
D2
I/O0 to I/O7
D11
/CS
/CS DQMB6
/CS
D3
DQM I/O0 to I/O7
D12
DQ48 to DQ55
DQM 8 N14, N15 I/O0 to I/O7
D7
DQM I/O0 to I/O7
D16
/CS DQMB3 DQ24 to DQ31 CKE0 CKE1 CLK0 DQM 8 N8, N9 I/O0 to I/O7
/CS
/CS DQMB7
/CS
D4
DQM I/O0 to I/O7
D13
DQ56 to DQ63 VCC
DQM 8 N16, N17 I/O0 to I/O7
D8
DQM I/O0 to I/O7
D17
CKE (D0 to D8) CKE (D9 to D17) CLK (D0, D1, D9,D10) CLK (D2, D5, D6, D11, D14, D15) CLK (D3, D4, D12, D13) CLK (D7, D8, D16, D17)
N18 to N21
VCC (D0 to D17) C18 to C56 VSS (D0 to D17) Serial PD SCL SCL A0 A1 A2 VSS U0 SDA SDA
VSS
CLK1
A0 to A9, A11 to A12 BA0, /RE, /CE, /W
VSS R0 to R1
C0 to C15
RA0 to RA9, RA11 to RA12 RBA0, /RRE, /RCE, /RW
A10, BA1
C16 to C17
RA10, RBA1
VSS
* D0 to D7: 256M bits SDRAM TCP R0 to R1: 22 N0 to N17: Network resistors (10) N18 to N21: Network resistors (22) C0 to C17: 20pF C18 to C56: 0.1F U0: 2k bits EEPROM
Data Sheet E0223H30 (Ver. 3.0)
7
HB52RF649DC-B, HB52RD649DC-B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC IOUT PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max.)) -0.5 to +4.6 50 9.0 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1
Note: 1. Respect to VSS.
DC Operating Conditions (TA = 0 to +65C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient illuminance VIH VIL -- min. 3.0 0 2.0 -0.3 -- max. 3.6 0 VCC + 0.3 0.8 100 Unit V V V V lx Note 1, 2 3 1, 4 1, 5
Notes: 1. 2. 3. 4. 5.
All voltage referred to VSS. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VCC + 2.0V for pulse width 3ns at VCC. VIL (min.) = VSS - 2.0V for pulse width 3ns at VSS.
Data Sheet E0223H30 (Ver. 3.0)
8
HB52RF649DC-B, HB52RD649DC-B
DC Characteristics 1 (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Parameter Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current (CL = 2) (CL = 3) Refresh current Self refresh current Self refresh current (L-version) Symbol ICC1 ICC1 ICC2P ICC2PS ICC2N ICC3P ICC3N ICC4 ICC4 ICC5 ICC6 ICC6 -75 -A6 -75 -A6 Grade -75 -A6 -75 -A6 Max. 1260 1125 1260 1125 54 36 360 72 540 1170 1170 1485 1170 2250 54 36 Unit mA mA mA mA mA mA mA mA mA mA mA mA tRC = min. VIH VCC - 0.2V VIL 0.2V 3 8 CKE0 = VIL, tCK = 12ns CKE0 = VIL, tCK = CKE0, /S = VIH, tCK = 12ns CKE0, /S = VIH, tCK = 12ns CKE0, /S = VIH, tCK = 12ns tCK = min., BL = 4 6 7 4 1, 2, 6 1, 2, 4 1, 2, 5 Test conditions Burst length = 1 tRC = min. Notes 1, 2, 3
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current.
DC Characteristics 2 (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL Grade min. -10 -10 2.4 -- Max. 10 10 -- 0.4 Unit A A V V Test conditions 0 Vin VCC 0 Vout VCC DQ = disable IOH = -4 mA IOL = 4 mA Notes
Data Sheet E0223H30 (Ver. 3.0)
9
HB52RF649DC-B, HB52RD649DC-B
Pin Capacitance (TA = 25C, VCC = 3.3V 0.3V)
Parameter Input capacitance Input capacitance Input capacitance Input capacitance Input/Output capacitance Symbol CIN CIN CIN CIN CI/O Pins Address /RE, /CE, /W, /S0, /S1, CK0, CK1, CKE0, CKE1 DQMB DQ, CB max. 110 110 65 30 27 Unit pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Notes: 1. 2. 3. 4.
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
AC Characteristics (TA = 0 to 65C, VCC = 3.3V 0.3V, VSS = 0V)
-75 Parameter System clock cycle time (CL = 2) (CL = 3) CK high pulse width CK low pulse width Access time from CK (CL = 2) (CL = 3) Data-out hold time CK to Data-out low impedance Symbol tCK tCK tCKH tCKL tAC tAC tOH tLZ PC100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh min. 10 7.5 2.5 2.5 -- -- 2.7 2 -- 1.5 1.5 0.8 67.5 45 20 20 15 15 1 -- max. -- -- -- -- 6 5.4 -- -- 5.4 -- -- -- -- 120000 -- -- -- -- 5 64 -A6 min. 10 10 3 3 -- -- 3 2 -- 2 2 1 70 50 20 20 20 20 1 -- max. -- -- -- -- 6 6 -- -- 6 -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1, 5 1 1 1 1 1 1 1 1 1 1 1, 2 Notes 1
CK to Data-out high impedance tHZ Input setup time tAS, tCS, Tsi tDS, tCES Tpde Thi Trc Tras Trcd Trp Tdpl Trrd
CKE setup time for power down tCESP exit tAH, tCH, Input hold time tDH, tCEH Ref/Active to Ref/Active tRC command period Active to Precharge command tRAS period Active command to column tRCD command (same bank) Precharge to active command tRP period Write recovery or data-in to tDPL precharge lead time Active (a) to Active (b) tRRD command period Transition time (rise and fall) Refresh period tT tREF
Data Sheet E0223H30 (Ver. 3.0)
10
HB52RF649DC-B, HB52RD649DC-B
Notes: 1. 2. 3. 4. 5. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V. Access time is measured at 1.5V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state. tCES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5V * Input waveform and output load: See following figures
2.4V
input
0.4V
2.0V 0.8V
I/O CL tT
tT
Input waveform and output load
Data Sheet E0223H30 (Ver. 3.0)
11
HB52RF649DC-B, HB52RD649DC-B
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CL = 2) (CL = 3) Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CL = 2) (CL = 3) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command /S to command disable Power down exit to command input Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lAPW lSEC lHZP lHZP lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lRSA lCDD lPEC Tccd Tdwd Tdqm Tdqz Tcke Tmrd Troh Troh Tsrx Tdal Tdpl PC100 Symbol -75 133 7.5 3 9 6 3 2 2 1 5 9 2 3 1 -1 -2 1 0 0 2 1 1 0 1 -A6 100 10 2 7 5 2 2 2 1 4 7 2 3 1 -1 -2 1 0 0 2 1 1 0 1 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Data Sheet E0223H30 (Ver. 3.0)
12
HB52RF649DC-B, HB52RD649DC-B
Pin Functions
CK0, CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /S0, /S1 (input pin): When /S is Low, the command input cycle becomes valid. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RE, /CE and /W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0, BA1(BA) is precharged. BA0, BA1 (input pin): BA0, BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is Low and BA1 is High, bank1 is selected. If BA0 is High and BA1 is Low, bank2 is selected. If BA0 is High and BA1 is High, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. CB0 to CB7 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.(E0082H)
Data Sheet E0223H30 (Ver. 3.0)
13
HB52RF649DC-B, HB52RD649DC-B
Physical Outline
Unit: mm 67.60 3.80 Max (Datum -A-) 2R3.00 Min
33.02
3.30
23.20 2.50 2.10
B 4.60
32.80
A 1.00 0.10
4.60 3.70 23.20 32.80
4.00 0.10
Component area (back) 2-R2.00
144
2
143
1
2.00 Min
Detail A
(Datum -A-) 0.60 0.05
Detail B
(DATUM -A-) 2.5 R0.75
2.55 Min
0.25 Max
0.80
4.00 0.10
3.20 Min
1.50 0.10
4.00 Min
20.00
Component area (front)
ECA-TS2-0042-02
Data Sheet E0223H30 (Ver. 3.0)
14
HB52RF649DC-B, HB52RD649DC-B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0223H30 (Ver. 3.0)
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HB52RF649DC-B, HB52RD649DC-B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0223H30 (Ver. 3.0)
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